A phase locked loop phase lock detector is used to determine when two periodic time-varying signals are "in phase," i.e., reaching the maximum and minimum values at the same time. A phase locked loop phase lock detector may be used in digital circuits to determine when the phase of an external digital signal is phase-aligned with the phase of a local oscillator. When the signals are phase-aligned, a phase lock signal is generated that may be used to enable any circuitry that requires the external signal to be phase-aligned with the local oscillator for proper function.
Phase lock may be spuriously indicated under several conditions. If a first signal is in phase with a second signal but has a frequency that is twice that of the second signal, then signal lock will be followed by loss-of-lock once each cycle. Random matches between asynchronous signals may also cause spurious lock indications. Likewise, other lock circuits may generate spurious lock indications. These spurious lock signals may cause the lock signal to "bounce" between a lock and unlock indication.
Such spurious lock indications may potentially cause misoperation of equipment, or increase equipment duty cycles. While some methods exist for detecting and "debouncing" spurious lock indications, such methods typically consist of waiting for an empirically-determined period of time until most spurious indications have been damped. This technique is not useful, however, when the frequency of one signal is twice the frequency of the other. Therefore, a need has arisen for a new method and circuit for detecting a spurious lock signal that overcomes the disadvantages and deficiencies of the prior art.